An LMS adaptive digital filter using distributed arithmetic (DA-ADF) has been proposed. Cowan and others proposed the DA adaptive algorithm with offset binary coding for the simple derivation of an algorithm and the use of an odd-symmetry property of adaptive function space (AFS). However, we indicated that a convergence speed of this DA adaptive algorithm degraded extremely by our computer simulations. To overcome these problems, we have proposed the DA adaptive algorithm generalized with two's complement representation and effective architectures. Our DA-ADF has performances of a high speed, small output latency, a good convergence speed, small-scale hardware and lower power dissipation for higher order, simultaneously. In this paper, we analyze a convergence condition of DA adaptive algorithm that has never been considered theoretically. From this analysis, we indicate that the convergence speed is depended on a distribution of eigenvalues of an auto-correlation matrix of an extended input signal vector . Furthermore, we obtain the eigenvalues theoretically. As a result, we clearly show that our DA-ADF has an advantage of the conventional DA-ADF in the convergence speed.

A power packet dispatching system is proposed to realize the function of power on demand. This system distributes electrical power in quantized form, which is called power processing. This system has extensibility and flexibility. Here, we propose to use the power packet dispatching system as the next generation power distribution system in self-established and closed system such as robots, cars, and aircrafts. This paper introduces the concept and the required researches to take the power packet dispatching system in practical phase from the total viewpoints of devices, circuits, power electronics, system control, computer network, and bio-inspired power consumption.

Performance of band-limited baseband synchronous CDMA using orthogonal Independent Component Analysis (ICA) spreading sequences is investigated. The orthogonal ICA sequences have an orthogonality condition in a synchronous CDMA like the Walsh-Hadamard sequences. Furthermore, these have useful correlation properties like the Gold sequences. These sequences are obtained easily by using the ICA which is one of the brain-style signal processing algorithms. In this study, the ICA is used not as a separator for received signal but as a generator of spreading sequences. The performance of the band-limited synchronous CDMA using the orthogonal ICA sequences is compared with the one using the Walsh-Hadamard sequences. For limiting bandwidth, a Root Raised Cosine filter (RRC) is used. We investigate means and variances of correlation outputs after passing the RRC filter and the Bit Error Rates (BERs) of the system in additive white Gaussian noise channel by numerical simulations. It is found that the BER in the band-limited system using the orthogonal ICA sequences is much lower than the one using the Walsh-Hadamard sequences statistically.

A high speed, 4 K word by one bit static Random Access Memory (RAM) has been developed, using Diffusion Self-Aligned (DSA) MOS technology. High speed and low power operation was achieved by combining the following refined devices and new circuit technology; high gain DSA MOS FETs as drivers, Reverse DSA (RDSA) MOS FETs with low threshold voltage (VTAR0 V) as power reduction switches, full wave rectifier substrate bias generator and dual X-decoder circuits. The present RAM operates on a single 51 V external power supply. Its typical performances are; 28 ns chip enable access time (CL33 pF), 300 mW active power dissipation and 50 mW stand-by power dissipation.

We describe wavelength-routed switching technology for 25-Gbit/s optical packets using a tunable transmitter that monolithically integrates a parallel-ring-resonator tunable laser and an InGaAlAs electro-absorption modulator (EAM). The transmitter provided accurate wavelength tunability with 100-GHz spacing and small output power variation. A 25-Gbit/s burst-mode optical-packet data was encoded onto the laser output by modulating the integrated EAM with a constant voltage swing of 2 V at 45$^{circ}$C. Clear eye openings were observed at the output of the 100 GHz-spaced arrayed-waveguide grating with error-free operation being achieved for all packets. The tunable transmitter is very promising for realizing a high-speed, large-port-count and energy-efficient wavelength-routing switch that enables the forwarding of 100-Gbit/s optical packets.

Asynchronous optical packet switching (OPS) is a promising solution to support the continuous growth of transmission capacity demand. It has been, however, quite difficult to implement key functions needed at the node of such networks with all-optical approaches. We have proposed a new optoelectronic system composed of a packet-by-packet optical clock-pulse generator (OCG), an all-optical serial-to-parallel converter (SPC), a photonic parallel-to-serial converter (PSC), and CMOS circuitry. The system makes it possible to carry out various required functions such as buffering (random access memory), optical packet compression/decompression, and optical label swapping for high-speed asynchronous optical packets.

Ultra-densification of radio access network (RAN) is essential to efficiently handle the ever-increasing mobile data traffic. In this paper, a joint multi-layered user clustering and scheduling is proposed as an inter-cluster interference coordination scheme for ultra-dense RAN using cluster-wise distributed MIMO transmission/reception. The proposed joint multi-layered user clustering and scheduling consists of user clustering using the K-means algorithm, user-cluster layering (called multi-layering) based on the interference-offset-distance (IOD), cluster-antenna association on each layer, and layer-wise round-robin-type scheduling. The user capacity, the sum capacity, and the fairness are evaluated by computer simulations to show the effectiveness of the proposed joint multi-layered user clustering and scheduling. Also shown are uplink and downlink capacity comparisons and optimal IOD setting considering the trade-off between inter-cluster interference mitigation and transmission opportunity.

This paper describes the modeling and the analysis methodology to evaluate Simultaneous Switching Noise (SSN) for the combined system of the package with the 4-layer Printed Circuit Board (PCB), which the 64 Simultaneous Switching Outputs (SSOs) were included using a simple IBIS model. Simulation results showed that the ground plane in both package and PCB can be used as the reference to reduce SSN more effectively than the power plane. For the source synchronous timing technique such as used in a DDR SDRAM memory bus in the model shown in this paper, the skew control circuit tequiniqe is easy to apply in the chip design instead of using embedded capacitors in the package's substrate. And also the radiated emission and eye diagram analysis were studied.

This paper describes a design of a Carry Propagation Free Adder/Subtracter (CPFA/S) VLSI using the Adiabatic Dynamic CMOS Logic (ADCL) circuit technology. Using a PSPICE simulator, energy dissipation of the ADCL 1 bit CPFA/S is compared with that of the CMOS 1 bit CPFA/S. As a result, energy dissipation of the proposed ADCL circuits is about 1/3 as high as that of the CMOS circuits. The transistors count, propagation-delay time and energy dissipation of the ADCL 4 bit CPFA/S are compared with those of the ADCL 4 bit Ripple Carry Adder/Subtracter (RCA/S). The transistors count and propagation-delay time are found to be reduced by 7.02% and 57.1%, respectively. Also, energy dissipation is found to be reduced by 78.4%. Circuit operation and performance are evaluated using a chain of the ADCL 1 bit CPFA/S fabricated in a 1.2 µm CMOS process. The experimental results show that addition and subtraction are operated with clock frequencies up to about 1 MHz. In addition, the total power dissipation of the ADCL 1 bit CPFA/S is 28.7 µW including the power supply.

A fast calculation tool for state-dependent capacitance of power distribution network is proposed. The proposed method achieves linear time-complexity, which can be more than four orders magnitude faster than a conventional SPICE-based capacitance calculation. Large circuits that have been unanalyzable with the conventional method become analyzable for more comprehensive exploration of capacitance variation. The capacitance obtained with the proposed method agrees SPICE-based method completely (up to 5 digits), and time-linearity is confirmed through numerical experiments on various circuits. The maximum and minimum capacitances are also calculated using average and variance estimation. Calculation times are linear time-complexity, too. The proposed tool facilitates to build an accurate macro model of an LSI.

The power packet dispatching system, in which electric power is transferred in a pulse-shaped form with information, is expected to realize dynamical management of multiple power sources in independent systems such as robots. In this letter, close-loop control of a stepper motor by power packets is discussed. The precise angle control is achieved by the combined transfer of power and control information in experiments.

Cell-free massive MIMO (CF-mMIMO), which cooperatively utilizes a large number of antennas deployed over a communication area, has been attracting great attention as an important technology for realizing 5G-advanced and 6G systems. Recently, to ensure system scalability and mitigate inter-user interference in CF-mMIMO, a user-centric (UC) approach was investigated. In this UC approach, user-centric antenna-sets are formed by selecting appropriate antennas for each user, and postcoding is applied to reduce the strong interference from users whose antenna-sets overlap. However, in very high user density environments, since the number of interfering users increases due to increased overlapping of antenna-sets, the achievable link capacity may degrade. In this paper, we propose a user-cluster-centric (UCC) approach, which groups neighborhood users into a user-cluster and associates the predetermined number of antennas to this user-cluster for spatial multiplexing. We derive the uplink postcoding weights and explain the effectiveness of the proposed UCC approach in terms of the computational complexity of the weight computation. We also compare the uplink user capacities achievable with UC and UCC approaches by computer simulation and clarify situations where the UCC approach is effective. Furthermore, we discuss the impact of the number of interfering users considered in the zero-forcing and minimum mean square error postcoding weight computation on the user capacity.

To cope with ever growing mobile data traffic, we recently proposed a concept of cellular ultra-dense radio access network (RAN). In the cellular ultra-dense RAN, a number of distributed antennas are deployed in the base station (BS) coverage area (cell) and user-clusters are formed to perform small-scale distributed multiuser multi-input multi-output (MU-MIMO) transmission and reception in each user-cluster in parallel using the same frequency resource. We also proposed a decentralized interference coordination (IC) framework to effectively mitigate both intra-cell and inter-cell interferences caused in the cellular ultra-dense RAN. The inter-cell IC adopted in this framework is the fractional frequency reuse (FFR), realized by applying the channel segregation (CS) algorithm, and is called CS-FFR in this paper. CS-FFR divides the available bandwidth into several sub-bands and allocates multiple sub-bands to different cells. In this paper, focusing on the optimization of the CS-FFR, we find by computer simulation the optimum bandwidth division number and the sub-band allocation ratio to maximize the link capacity. We also discuss the convergence speed of CS-FFR in a cellular ultra-dense RAN.

In this study, an overloaded large-scale distributed antenna network is considered, for which the number of active users is larger than that of antennas distributed in a base station coverage area (called a cell). To avoid overload, users in each cell are divided into multiple user groups, and, to reduce the computational complexity required for multi-user multiple-input and multiple-output (MU-MIMO), users in each user group are grouped into multiple user clusters so that cluster-wise distributed MU-MIMO can be performed in parallel in each user group. However, as the network size increases, conventional computational methods may not be able to solve combinatorial optimization problems, such as user scheduling and user clustering, which are required for performing cluster-wise distributed MU-MIMO in a finite amount of time. In this study, we apply quantum computing to solve the combinatorial optimization problems of user scheduling and clustering for an overloaded distributed antenna network and propose a quantum computing-based user scheduling and clustering method. The results of computer simulations indicate that as the technology of quantum computers and their related algorithms evolves in the future, the proposed method can realize large-scale dense wireless systems and realize real-time optimization with a short optimization execution cycle.

In this study, a performance of a synchronous code division multiple access (CDMA) using the chaotic spreading sequences with constant power is estimated in indoor power line fading channels. It is found that, in the fading channels, as the number of simultaneous users increases, the chaotic spreading sequences realize better performance than the Walsh-Hadamard sequences in the synchronous CDMA.

A power allocation to active and reactive power in stochastic resonance is discussed for energy harvesting from noise. It is confirmed that active power can be increased at stochastic resonance, in the same way of the relationship between energy and phase at an appropriate setting in resonance.

Power packet is a unit of electric power transferred by a pulse with an information tag. This letter discusses up-stream dispatching of required power at loads to sources through density modulation of power packet. Here, power is adjusted at a proposed router which dispatches power packets according to the tags. It is analyzed by averaging method and numerically verified.

In this letter, we establish a model of a digital clock synchronization method for power packet dispatching. The first-order control is carried out to a specified model to achieve the clock synchronization. From the experimental results, it is confirmed that power packets were recognized under autonomous synchronization.

In this paper, the measurement of capacitance variation, of an on-chip power distribution network (PDN) due to the change of internal states of a CMOS logic circuit, is studied. A state-dependent PDN-capacitance model that explains measurement results will be also proposed. The model is composed of capacitance elements related to MOS transistors, signal and power supply wires, and substrate. Reflecting the changes of electrode potentials, the capacitance elements become state-dependent. The capacitive elements are then all connected in parallel between power supply and ground to form the proposed model. By using the proposed model, state-dependence of PDN-capacitances for different logic circuits are studied in detail. The change of PDN-capacitance exceeds 12% of its total capacitance in some cases, which corresponds to 6% shift of anti-resonance frequency. Consideration of the state-dependence is important for modeling the PDN-capacitance.

An optoelectronic 32-bit serial-to-parallel converter with a novel conversion scheme and shared-trigger configuration has been developed for the label processing of 100-Gbps (25-Gbps $ imes 4 lambda)$ optical packets. No external optical trigger source is required to operate the converter, as the optical packet itself is used to perform self-triggering. Compared to prior optoelectronic label converters, the new device has a much higher gain even while converting labels at higher data rates, and exhibits tolerance to the voltage swing of received packets. The device response is presented together with the experimental demonstration of serial-to-parallel conversion for 4 different labels at 25 Gbps.